A MOS-Based Temperature Sensor With Inherent Inaccuracy Reduction Enabled by Time-Domain Operation

This article presents a MOS-based ON-chip temperature sensor system addressing both high-resolution and lowinaccuracy requirement, red while requiring a single temperature calibration point. Hence, the proposed temperature sensor system proves to be a low-cost solution, well addressing the requirements of the spreading market of system-on-chips (SoCs), mobile and wearable devices, and consumer electronics in general. The temperature sensor features a two-phase time-domain architecture, which employs as a sensing element a single NMOS transistor, biased alternatively with different currents, thus allowing achieving an inherent inaccuracy reduction. The proposed sensory system, fabricated in a standard 130-nm CMOS process, comprises, along the sensor core, a switched-capacitor analog interface circuit and a 1-bit second-order sigma-delta (61) analog-to-digital converter (ADC). The proposed temperatureto-digital converter (TDC), experimentally characterized considering a batch of 16 samples, achieves 40-mK resolution at 20-kHz switching frequency and +0.75/-0.92. C inaccuracy across the -40 degrees C-90 degrees C temperature range after one-point calibration at room temperature, consuming 25.4 mu W, including the analog buffer added for testing purposes.

Automated summary

This article introduces a MOS-based on-chip temperature sensor system that meets both high-resolution and low inaccuracy requirements, with only one temperature calibration point. Therefore, the proposed temperature sensor system is a low-cost solution that can effectively address the needs of the expanding market for system-on-chips (SoCs), mobile and wearable devices, and consumer electronics. The temperature sensor utilizes a two-phase time-domain architecture, with a single NMOS transistor as the sensing element biased alternately with different currents to achieve inherent inaccuracy reduction. The proposed sensory system, fabricated in a standard 130-nm CMOS process, includes a switched-capacitor analog interface circuit and a 1-bit second-order sigma-delta (ΣΔ) analog-to-digital converter (ADC) in addition to the sensor core.