Reliability challenges in Forksheet Devices

The forksheet (FSH) device architecture is a possible candidate towards continued logic cell downscaling. It consists of vertically stacked n- and ptype sheets at opposing sides of a dielectric wall. In this work, we overview the time-0 and time-dependent performance of n and p-type FSH field-effect transistors co-integrated with nanosheets (NSH) in individual wafers. A separate assessment of dedicated capacitors yields indications of a non-negligible effect of negative fixed charges trapped in low-temperature deposited SiO2, currently used as dielectric wall liner. Finally, we evaluate the impact of using a bottom dielectric isolation (BDI) instead of a junction-based electrical isolation of the sheets from the substrate.

Automated summary

This study summarizes the time-0 and time-dependent performance of n and p-type FSH field-effect transistors, as well as the separate assessment of NSH chips. Additionally, the impact of using a bottom dielectric isolation instead of junction-based electrical isolation is evaluated.