A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on a Reconfigurable SRAM Sense Amplifier

In this paper, a hybrid memory architecture based on a new array of SRAM and resistive random-access memory (RRAM) cells is proposed to perform in-memory computing by implementing all basic two-input Boolean functions. The SRAM array can be configured as a dual-purpose element. It can be used as an SRAM array in memory mode to keep data for high-performance application requirements. It can also be configured as a sense amplifier (SA-SRAM) for reading the contents of RRAMs and performing the in-memory computation. The circuits are designed using independent-gate FinFET (IG-FinFET), whose channel is controlled by two independent gates, increasing the design's maneuverability. Our results indicate that the proposed SA-SRAM cells' write energy consumption and combined word line margin (CWLM) achieve 50% and 20% improvements compared to the conventional 8T SRAM. Moreover, by benefiting from the combination of SRAM and RRAM cells in the proposed architecture, the energy consumption of our design in application areas, such as image processing, is much lower than the well-known compared in-memory architecture designs. In addition, to address security concerns, we proposed a polymorphic circuit primitive to prevent reverse engineering or integrated circuit (IC) counterfeiting. The proposed polymorphic circuit also adds more computations to accomplish complex logic operations and the proposed hybrid memory architecture.

Automated summary

A hybrid memory architecture based on SRAM and RRAM cells is proposed for in-memory computing. The SRAM array can be used as an SRAM array in memory mode or as a sense amplifier for reading RRAM contents and performing in-memory computation. The design utilizes independent-gate FinFET for increased maneuverability. Experimental results show improvements in write energy consumption and combined word line margin compared to conventional SRAM, and lower energy consumption in application areas compared to other in-memory architectures. Additionally, a polymorphic circuit is proposed for security purposes.