3.8 Proceedings Paper

SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP

Publisher

ASSOC COMPUTING MACHINERY
DOI: 10.1145/3583781.3590225

Keywords

processing in-sensor; multi-layer perceptron; low-power CMOS imager

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In this paper, we propose an ultra-low-power in-sensor architecture called SenTer, which enables low-precision ternary multi-layer perceptron networks in detection and classification modes. SenTer supports two activation functions and significantly reduces overhead by performing computations in the analog domain and using only one ADC. Our simulation results show acceptable accuracy compared to full precision models on various datasets.
Recently, Intelligent IoT (IIoT), including various sensors, has gained significant attention due to its capability of sensing, deciding, and acting by leveraging artificial neural networks (ANN). Nevertheless, to achieve acceptable accuracy and high performance in visual systems, a power-delay-efficient architecture is required. In this paper, we propose an ultra-low-power processing in-sensor architecture, namely SenTer, realizing low-precision ternary multi-layer perceptron networks, which can operate in detection and classification modes. Moreover, SenTer supports two activation functions based on user needs and the desired accuracy-energy trade-off. SenTer is capable of performing all the required computations for the MLP's first layer in the analog domain and then submitting its results to a co-processor. Therefore, SenTer significantly reduces the overhead of analog buffers, data conversion, and transmission power consumption by using only one ADC. Additionally, our simulation results demonstrate acceptable accuracy on various datasets compared to the full precision models.

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