Reconfigurable Leakage-based Weak PUF in 65nm CMOS with 0.63% instability

Reliability of hardware security devices is of paramount importance when deployed in a System-On-Chip along-with the IoT sensor nodes. A bit flip could cause the node to be unrecognizable by the trusted source and increase costs due to replacement and re-deployment. To tackle these problems we fabricate a weak PUF in 65nm CMOS which can be used for chip ID applications. The design is based on OFF devices which consume only leakage current, and more importantly, provide large drain current mismatch and therefore output voltage dispersion. This large dispersion results in lower instability and Bit Error Rate (BER), making the design ideal for integration with IoT devices. To this end we measure instability of 2.81% over 2000 evaluations, and native BER of 0.48%. Native BER is below 2.5% over both temperature (-4080 degrees C) and voltage range (0.8-1.2V). Additionally, reconfiguration aids in reducing the instability/BER to 0.63%/0.047%, implying excellent reproducibility of the key. High throughput of 9.6 Gb/s is measured by implementing SRAM-style array for parallel readout. Core energy/bit is measured to be 5.99 fJ/bit.

Automated summary

The reliability of hardware security devices in a System-On-Chip with IoT sensor nodes is crucial. A weak PUF fabricated in 65nm CMOS is designed for chip ID applications, utilizing OFF devices to achieve low instability and BER. The measurements show high reproducibility and throughput, making it a promising choice for integration with IoT devices.