A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor

This article presents a 12-bit 1-GS/s ring-amp-based analog-to-digital converter (ADC) with a pipelined and time-interleaved successive approximation register (TI-SAR) hybrid architecture. This architecture utilizes backend time-interleaving for power and design complexity reduction while eliminating the sampling time skew. A ring amplifier (ring-amp) is used in this architecture to significantly reduce the power of residue amplification by about ten times over a prior work. A high-speed PVT-robust ring-amp with split input by splitting the multiplying DAC (MDAC) is proposed to guarantee the performance of the ring-amp under low supply voltage. To improve the power supply rejection ratio (PSRR) of the reference buffer and lower the reference noise without degrading the reference settling speed, a switched reference decoupling capacitor (de-cap) technique is proposed. Flash ADC and backend successive approximation register (SAR) ADCs are also optimized to meet the challenging power efficiency requirement. The ADC implemented in a 28-nm CMOS process achieves 62.5-dB SNDR for Nyquist input. The total power including the reference buffer is 10.6 mW, yielding a Schreier figure of merit (FoMS) of 169.2 dB.

Automated summary

This article presents a 12-bit 1-GS/s ADC with a hybrid architecture utilizing a pipelined and time-interleaved SAR. It uses backend time-interleaving to reduce power and design complexity, while eliminating sampling time skew. The architecture incorporates a ring amplifier (ring-amp) to reduce the power of residue amplification, and a PVT-robust ring-amp with split input is proposed to ensure performance under low supply voltage. A switched reference decoupling capacitor technique is also introduced to improve PSRR and reduce reference noise. The implemented ADC achieves a SNDR of 62.5 dB and a FoMS of 169.2 dB.