Journal
SCIENCE CHINA-INFORMATION SCIENCES
Volume 59, Issue 12, Pages -Publisher
SCIENCE PRESS
DOI: 10.1007/s11432-015-5475-7
Keywords
charge trapping memory; semiconductor device modeling; 2-D charge transport; 3-D NAND flash; device modeling and simulation
Funding
- National Natural Science Foundation of China [91230107]
- National Basic Research Program of China (973) [2013CBA01604]
- National High Technology Research and Development Program of China (863) [2015AA016501]
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This work presents a self-consistent two-dimensional (2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data, which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory.
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