Identification of grain boundaries as degradation site in n-channel organic field-effect transistors determined via conductive atomic force microscopy

One important figure of merit for the commercial usability of organic transistors (OFETs) is their electrical stability. With the aim of identifying the microscopic location of degradation sites within a transistor channel, we have investigated the bias stress stability of OFETs by electrical measurements as well as by conductive atomic force microscopy. Air-stable n-channel FETs based on a N,N-bis(2-ethylhexyl)-1,7(1,6)-dicyano-perylene[3,4:9,10]bis (dicarboximide) were fabricated to understand the relation between the thin-film morphology, the substrate temperature during the vacuum de position with the aim to fabricate transistors with a mobility not dominated by interface traps. The devices showed a maximum carrier mobility of (0.12 +/- 0.01) cm(2)/V s and an on/off ratio up to 10(7). The electrical performance as well as the bias stress behavior of the semiconductor thin-films is significantly influenced by grain boundaries. For example, the grain boundary resistance was found to increase upon electrical stress by more than 150% (from 2 +/- 0.2 G to 5 +/- 1.5 G), while the resistance within the grains remains unchanged. (C) 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim