Four stage CMOS operational amplifier, frequency compensated via active miller network

A four-stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well-known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 mu m CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four-stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC-gain, 10 MHz as unity gain frequency with power consumption less than 500 mu W.

Automated summary

This work proposes a four-stage CMOS operational amplifier that is frequency compensated via two differential blocks and two Miller capacitors. Unlike conventional approaches, the proposed compensation method uses extremely smaller capacitors but still maintains the output node. The simulation results demonstrate that the proposed amplifier is an excellent option for larger systems, with high DC-gain, unity gain frequency, and low power consumption.