4.7 Article

Fabrication of Embedded Microfluidic Chips with Single Micron Resolution Using Two-Photon Lithography

Journal

ADVANCED MATERIALS TECHNOLOGIES
Volume -, Issue -, Pages -

Publisher

WILEY
DOI: 10.1002/admt.202300667

Keywords

deterministic lateral displacement; developing of sub 100 mu m channels; droplet generators; microfluidics; two-photon lithography

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Two-photon lithography is an advanced additive manufacturing technique that can produce high-resolution objects with micro-scale features. In this study, a process flow was developed to fabricate embedded microfluidic chips with nanoscale channels, and a method for washing the channels effectively was introduced. This technique allows for the rapid production of different types of microfluidic chips, reducing the time from design to manufacturing.
Two-photon lithography (TPL) is an advanced high-resolution additive manufacturing technique for objects with feature sizes between 100 nanometers to tens of micrometers and an overall footprint of up to hundreds of micrometers. With recent advances in the TPL technique, writing speeds are becoming faster, rendering the method feasible to print high-resolution microfluidic chips with a footprint in the centimeter range within a reasonable time frame. In this work, a process flow to fabricate embedded microfluidic chips with channel diameters down to 30 mu m is developed. To address the particular difficulty of washing the embedded channels free of uncured material, introduces a developing scheme based on a 3D printed chip-to-world-interface to connect the chips to a pressure-driven pump. This setup is leakage-free up to a pressure of 6.9 bar for faster and safer development of embedded microfluidic devices. It manufactures meander chips with channel lengths up to 20 cm, droplet generator chips, and cell sorting chips based on deterministic lateral displacement with pillar diameters of 30 mu m and pillar spacing of 4 mu m. TPL of microfluidic chips will enable rapid manufacturing of novel designs, significantly reducing concept-to-chip times with high resolution in a reasonable amount of time.

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