Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n(+)-drain is presented in this paper. Two highly-doped p(+) silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as I-on=34.4 mu A/mu m, I-on/I-off=7.17x10(7), and f(T)=123 GHz show that our proposed device is a notable candidate for both DC and RF applications.

Automated summary

This paper presents a vertical tunneling field effect transistor with a doping-less tunneling heterojunction and an n(+)-drain. The optimized electrostatic control over the channel is achieved through a double gate configuration and Hafnium in the gate oxide. Numerical simulations and evaluations of non-idealities demonstrate that the proposed device is a notable candidate for both DC and RF applications.