Spatially Resolved Probabilities of Stacking Fault Formation in SiC Nanowires for Probing Growth Conditions

Spatially resolved probabilities of stacking fault formation in SiC nanowires were determined along the growth axis using transmission electron microscopy. The analysis revealed that the probability changed during nanowire growth. It is most likely that the change in the probability of stacking fault formation was due to the changes in the growth temperature and/or the degree of supersaturation of the source materials vapor. In addition, Y-shaped side-by-side nanowire pairs showed large decreases at the junctions presumably due to the effects of stress and/or distortion at the junctions.

Automated summary

Transmission electron microscopy was used to determine the spatially resolved probabilities of stacking fault formation along the growth axis of SiC nanowires. The analysis revealed that the probability changed during nanowire growth, most likely due to changes in growth temperature and/or supersaturation of the source materials vapor. Additionally, Y-shaped side-by-side nanowire pairs showed significant decreases at the junctions, presumably due to stress and/or distortion effects.