Design of a high-accuracy time-to-digital converter based on dual-edge signals

Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates. Limited by the device process, the delay of each cell in the TDL exhibits a random and uneven distribution, degrading the linearity of the TDC. In this study, a dual-edge TDL structure is proposed. By improving original pulse-holding circuit, the propagated signal injected into the fine measurement chain is alternately switched between rising and falling edge signals to decrease the dead time to one cycle. The nonlinearity problem is alleviated by an enhanced tapped sampling sequence circuit. A dual-edge 1 count encoder is introduced to effectively simplify the difficulty of addressing the bubble problem. Bit-by-bit calibration and a moving average filter are adopted to improve accuracy. The proposed scheme has been verified on a Xilinx Kintex-7 FPGA platform. The resolution (least significant bit, LSB1) is 12.07 ps when the propagated signal in the TDL is the rising edge. The differential nonlinearity (DNL) is [-0.81, 0.93] LSB1, and the integral nonlinearity (INL) is between [-2.33, 2.19] LSB1. At the falling edge, the resolution (LSB0) is 11.90 ps, between [-0.73, 0.98] LSB0 and [-2.46, 1.83] LSB0 for DNL and INL, respectively. In addition, the accuracy reaches 15.25 ps after multiple measurements for different time intervals separately.

Automated summary

In this study, a new dual-edge TDL structure is proposed to improve the performance of TDC. By improving the original pulse-holding circuit and using an enhanced sampling sequence circuit, the proposed scheme achieves good results in terms of resolution and accuracy.