Journal
MICROELECTRONICS JOURNAL
Volume 48, Issue -, Pages 109-119Publisher
ELSEVIER SCI LTD
DOI: 10.1016/j.mejo.2015.11.009
Keywords
MTCMOS; Data stability; Static noise margin; Write voltage margin; Write assist transistor; Leakage power consumption; Data retention SLEEP mode; Process parameter variations; Minimum power supply voltage
Ask authors/readers for more resources
Multi-threshold CMOS (MTCMOS) technique is commonly used for suppressing leakage currents in idle circuits. The application of MTCMOS technique to static random access memory (SRAM) circuits is investigated in this paper. Two asymmetrically ground-gated MTCMOS SRAM circuits are presented for providing a low-leakage SLEEP mode with data retention capability. The read and hold static noise margins are increased by up to 7.24 x and 2.39 x, respectively, with the new asymmetrical SRAM cells as compared to conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. The overall electrical quality of a memory array is enhanced by up to 103.52 x and 57.75% with the proposed asymmetrically ground-gated memory cells as compared to the conventional ground-gated 6T and eight transistor (8T) SRAM cells, respectively. The new asymmetrical SRAM cells also exhibit enhanced tolerance to process parameter variations and lower minimum applicable power supply voltages as compared with the conventional 6T and 8T SRAM cells. (C) 2015 Elsevier Ltd. All rights reserved.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available