A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-μm CMOS process

In the design of CMOS optical receivers, it is challenging to compromise the bandwidth, noise, and gain of the transimpedance amplifier (TIA). The inverter-based cascaded structure is often used in TIA designs. However, the traditional 3-stage TIA needs bandwidth expansion techniques to get good performance. In the designed front-end, we propose a 5-stage cascaded TIA that achieves performance improvement without using bandwidth expansion technique. Besides, the stability of the main amplifier (MA) is improved by adopting a feed-forward compensation technique. Designed in a 0.13-mu m CMOS process, the proposed front-end exhibits a bandwidth root of 8.9 GHz, a transimpedance gain of 123.5 dB omega and an average input-referred noise of 12.2 pA/ Hz. The whole circuit consumed 19.1 mW from mixed input of 1 V and 1.5 V supply voltages.

Automated summary

In the design of CMOS optical receivers, it is challenging to balance the bandwidth, noise, and gain of the transimpedance amplifier (TIA). This study proposes a 5-stage cascaded TIA to improve performance without using bandwidth expansion techniques.