A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (<2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5 x 1.5 mm including a matrix of 32 x 32 pixels with a pitch of 15 mu m. The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42 mu m(2) and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design.

Automated summary

This article presents the design of a front-end circuit for monolithic active pixel sensors. The circuit operates with a sensor featuring a small, low-capacitance collection electrode and is integrated into the DPTS chip. The chip, implemented in 65-nm imaging technology, was developed to explore this technology for particle detection. The front-end circuit has a small area and low power consumption.