4.6 Article

An Integrated Reconfigurable Spin Control System on 180 nm CMOS for Diamond NV Centers

Journal

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Volume 71, Issue 9, Pages 4052-4063

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TMTT.2023.3254600

Keywords

Qubit; Delays; Microwave oscillators; Diamonds; Semiconductor device measurement; Microwave filters; Microwave amplifiers; CMOS integrated circuits; microwave; nitrogen-vacancy (NV) center; quantum computing; qubit

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In this paper, an integrated reconfigurable quantum control system is reported, which is used to find electron-spin resonance (ESR) frequency and perform Rabi, Ramsey, and Hahn-echo measurements for a nitrogen-vacancy (NV) center spin qubit in diamond. The chip can be programmed to synthesize an RF signal tunable from 1.6 to 2.6 GHz, which is modulated with a sequence of up to 4098 reconfigurable pulses with a pulse width and pulse-to pulse delay adjustable from 10 ns to 42 ms and 18 ns to 42 ms, respectively, at a resolution of 2.5 ns. The 180-nm CMOS chip is fabricated within a footprint of 3.02 mm(2) and has a power consumption of 80 mW.
Solid-state electron spins are key building blocks for emerging applications in quantum information science, including quantum computers, quantum communication links, and quantum sensors. These solid-state spins are mainly controlled using complex microwave pulse sequences, which are typically generated using benchtop electrical instruments. Integration of the required electronics will enable realization of a scalable low-power and compact optically addressable quantum system. Here, we report an integrated reconfigurable quantum control system, which is used to find electron-spin resonance (ESR) frequency and perform Rabi, Ramsey, and Hahn-echo measurements for a nitrogen-vacancy (NV) center spin qubit in diamond. The chip can be programmed to synthesize an RF signal tunable from 1.6 to 2.6 GHz, which is modulated with a sequence of up to 4098 reconfigurable pulses with a pulse width and pulse-to pulse delay adjustable from 10 ns to 42 ms and 18 ns to 42 ms, respectively, at a resolution of 2.5 ns. The 180-nm CMOS chip is fabricated within a footprint of 3.02 mm(2) and has a power consumption of 80 mW.

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