Circuit-Level Memory Cell Simulation of Magnetic Bloch Line Racetrack Memory

The Bloch line (BL) racetrack memory (RTM) has recently been proposed as a novel device to overcome the problems of the conventional domain wall (DW) RTM such as stochastic shift and high shift threshold current due to process-induced roughness. In this work, we assess the performance of BL RTM memory cells by conducting circuit-level simulations. A micromagnetics-SPICE hybrid simulation framework is proposed and implemented as an optimal solution to guarantee both computational efficiency and micromagnetics-level accuracy. The feasibility of multibit BL memory operations is demonstrated as the stochastic Landau-Lifshitz-Gilbert (s-LLG) and Monte-Carlo (MC) simulations are carried out at room temperature to take into account the temperature effect and process-induced device mismatch. Furthermore, some crucial considerations in designing and optimizing the BL memory are addressed.

Automated summary

This work assesses the performance of Bloch line (BL) racetrack memory (RTM) through circuit-level simulations. A micromagnetics-SPICE hybrid simulation framework is proposed to guarantee both computational efficiency and micromagnetics-level accuracy. The feasibility of multibit BL memory operations is demonstrated, and some crucial considerations in designing and optimizing the BL memory are addressed.