Repetitive ESD-Induced Electrical Degradation and Optimization for High-Voltage SOI-LIGBT as Output Device

In our work, the reliabilities and inner mechanisms of the high-voltage silicon-on-insulator lateral insulated gate bipolar transistors (SOI-LIGBTs) have been investigated comprehensively under the repetitive electro-static discharge (ESD) stresses for better application on the high-voltage circuits. The worst repetitive ESD stress occurs when the SOI-LIGBT is getting snapback with the turn-ON of the parasitic transistor. In the worst transmission line pulse (TLP) stress I, the ON-state voltage (V-on) and collector-to-emitter current density (J(ce)) are decreased as the stressing times. The decreased Von is attributed to the hot-hole injection at the gate plate edge, while the decreased Jce is attributed to the interface states generation at the gate plate edge and collector plate edge. The V-on decrease is better for SOI-LIGBT, but the decreased J(ce) is the opposite. To restrain the J(ce) degradation, the P-top layer structure has been proposed and fabricated with the same mask of the P-body. Then, the measured J(ce) degradation shows effective improvement of the proposed device due to its remarkable weakness for the hot-carrier effects.

Automated summary

In this study, the reliabilities and inner mechanisms of high-voltage silicon-on-insulator lateral insulated gate bipolar transistors (SOI-LIGBTs) under repetitive electro-static discharge (ESD) stresses were comprehensively investigated for better application in high-voltage circuits. It was found that the worst repetitive ESD stress occurred when the SOI-LIGBT was snapbacked with the turn-ON of the parasitic transistor. The ON-state voltage (V-on) and collector-to-emitter current density (J(ce)) decreased as the stressing times due to hot-hole injection and interface states generation. To mitigate the degradation of J(ce), a P-top layer structure was proposed and fabricated, which showed effective improvement in reducing the hot-carrier effects.