4.5 Article

TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs

Journal

IEEE TRANSACTIONS ON COMPUTERS
Volume 72, Issue 8, Pages 2306-2320

Publisher

IEEE COMPUTER SOC
DOI: 10.1109/TC.2023.3248269

Keywords

3DIC; IP authentication; IP piracy; logic locking; reverse-engineering

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The adoption of non-traditional design techniques by chip designers is driven by the need to meet growing user requirements and manufacturing challenges at lower technology nodes. Popular in recent years, 2.5D/3DIC stacking allows chip manufacturers to integrate complex IPs without design penalties. However, a completely untrusted supply chain poses challenges for verification and testing, making trust assurance of these designs difficult.
The push to meet growing user requirements and manufacturing challenges at lower technology nodes have motivated chip designers to adopt non-traditional design techniques. 2.5D/3DIC stacking has gained popularity in recent years since it enables chip manufacturers to integrate complex IPs to meet user demands without incurring design penalties. However, the non-traditional nature of the supply chain also means that additional challenges exist for verification and testing of the manufactured design, making the trust assurance of these designs an extremely challenging proposition. While there have been works focussing on securing 3DIC designs, very few address a completely untrusted supply chain. A robust security countermeasure must address the diverse trust requirements of the IPs in the design and the distributed supply chain requirements while ensuring that the functionality and performance overheads of the IC are not violated. We present TREEHOUSE, a trust assurance solution to counter piracy, reverse-engineering, and counterfeiting attacks. TREEHOUSE uses scan authentication to detect piracy and counterfeiting, scan-and functional-locking to prevent reverse-engineering. We evaluate the efficiency of our proposed scheme on an example 3DIC design. We show that TREEHOUSE incurs less than 1% area and power overheads while incurring less than 1% increase in overall gate count for each layer.

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