Data-Driven Feature Selection Framework for Approximate Circuit Design

The ever-growing data scale and computation complexity raise tremendous concerns about computer systems' efficiency (i.e., lower hardware overhead and power consumption). Orthogonal to the advancement in semiconductor manufacturing technologies, approximate computing provides an alternative paradigm to reduce the hardware cost and power dissipation by relaxing computation quality for error-resilient applications. Voltage over-scaling (VOS) and approximate logic design (ALD) have become two mainstream approaches of approximate computing due to their superior performance in efficiency-critical designs. VOS reduces the power in quadratic by scaling down supply voltage while ALD saves hardware overhead by redesigning an approximate version of a given circuit (e.g., trimming less significant circuitry). However, these primitive approximate circuits (PACs) inevitably introduce notable errors and require additional error compensation circuits (ECCs) to preserve computation accuracy. In existing works of ECC design, there lacks a systematic method that can generalize well to different approximate computing approaches. In this article, we present a data-driven feature selection framework for approximate circuit design, which is applicable to both VOS and ALD. We propose novel algorithms that profoundly analyze the correlation between input data and output errors and select the most critical features to generate compensation circuits. Extensive evaluations are performed over a variety of circuits using approximate finite impulse response (FIR) filters and the prevalent approximate computing benchmark AxBench. The experimental results show that the proposed approach achieves superior compensation performance, boosting the circuit accuracy while only introducing trivial area overhead.

Automated summary

This article presents a data-driven feature selection framework for approximate circuit design, applicable to both voltage over-scaling (VOS) and approximate logic design (ALD). Novel algorithms are proposed to analyze the correlation between input data and output errors and select critical features for generating compensation circuits. Extensive evaluations show that the proposed approach achieves superior compensation performance with minimal area overhead.