Journal
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume 42, Issue 8, Pages 2618-2630Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2022.3225066
Keywords
Bayesian optimization (BO); circuit design automation; machine learning; process variation; read access yield; static random-access memory (SRAM)
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This article presents an efficient yield estimation method for C-MPFP using Bayesian optimization to estimate PDF. The proposed method significantly reduces computational cost while maintaining accuracy. Experimental results show that the proposed method reduces simulation time by more than 20 times compared to BMC. Additionally, a BO-based design optimization method for static random-access memory read access is proposed, resulting in a 10% faster speed.
This article presents an efficient yield estimation method for the compensated-most probable failure point (C-MPFP) with the probability density function (PDF) estimation. Bayesian optimization (BO) is used to estimate the PDF. The computational cost can be significantly reduced using this method, while maintaining the accuracy. Our experimental results demonstrate that the proposed yield estimation method can reduce the simulation time by more than 20 times compared with the Brute force Monte Carlo (BMC). In addition, the BO-based automated static random-access memory read access design optimization method is proposed. The optimized design found by the proposed method demonstrates a 10% faster speed than arbitrarily selected designs while satisfying the target yield constraint. Consequently, the proposed design optimization process can efficiently reduce the computational cost of yield estimation for a given design as well as effectively reducing the number of times yield estimation is invoked with BO.
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