Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume -, Issue -, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2023.3289256
Keywords
Analog-to-digital converter (ADC); successive approximation register (SAR); delta-sigma modulator (DSM); noise shaping (NS); finite impulse response (FIR); error-feedback (EF)
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This article presents a single-loop third-order discrete-time delta-sigma modulator with a 4-bit second-order noise shaping successive approximation register quantizer. A novel finite impulse response filter is embedded in the noise shaping successive approximation register to achieve an aggressive noise transfer function. The prototype modulator achieves a peak Schreier figure of merit of 177.9 dB and a signal-to-noise and distortion ratio of 91.3 dB at an oversampling ratio of 64, with a power consumption of 44 μW.
This article presents a single-loop third-order discrete-time delta-sigma modulator (DTDSM) with a 4-bit second-order noise shaping successive approximation register (NS SAR) quantizer. To realize an aggressive noise transfer function (NTF), a novel Finite Impulse Response (FIR) filter is embedded in the NS SAR. As employing a flipped voltage follower (FVF), which offers unity gain instead of an open loop dynamic amplifier, the proposed FIR filter is sharp and insensitive to process, voltage, and temperature (PVT) variation. Fabricated in a 65-nm 1P9M CMOS technology, the prototype DTDSM consumes 44 mu W when operating at a 1.2-V supply voltage and a sampling rate of 2.4 MS/s. It achieves a peak Schreier figure of merit (FoM) of 177.9 dB with a signal-to-noise and distortionratio (SNDR) of 91.3 dB at an oversampling ratio (OSR) of 64.
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