Modeling and Predicting Transistor Aging Under Workload Dependency Using Machine Learning

The pivotal issue of reliability is one of the major concerns for circuit designers. The driving force is transistor aging, dependent on operating voltage and workload. At the design time, it is difficult to estimate close-to-the-edge guardbands that keep aging effects during the lifetime at bay. This is because the foundry does not share its calibrated physics-based models, comprised of highly confidential technology and material parameters. However, the unmonitored yet necessary overestimation of degradation amounts to a performance decline, which could be preventable. Furthermore, these physics-based models are computationally complex. The costs of modeling millions of individual transistors at design time can be exorbitant. We propose the use of a machine learning model trained to replicate the physics-based model, such that no confidential parameters are disclosed. This effectual workaround is fully accessible to circuit designers for the purposes of design optimization. We demonstrate the model's ability to generalize by training on data from one circuit and applying it successfully to a benchmark circuit. The mean relative error is as low as 1.7%, with a speedup of up to 20 x. Circuit designers, for the first time ever, will have ease of access to a high-precision aging model, which is paramount for efficient designs. In contrast to existing work, our approach takes the full switching activity into account to model recovery effects. This work is a promising step in the direction of bridging the gap between the foundry and circuit designers.

Automated summary

The reliability of circuit design is a major concern due to transistor aging, which is influenced by operating voltage and workload. The challenge lies in estimating close-to-the-edge guardbands for aging effects, as foundries do not disclose their confidential physics-based models. We propose a machine learning model that replicates the physics-based model without revealing confidential parameters, providing circuit designers with an accessible and efficient aging model. Our approach incorporates full switching activity to consider recovery effects, achieving a mean relative error as low as 1.7% and a speedup of up to 20 x. This work bridges the gap between foundries and circuit designers, offering a promising solution.