4.7 Article

An Energy Efficient Coherent IR-UWB Receiver With Non-Coherent-Assisted Synchronization

Journal

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2023.3281525

Keywords

Ultra-wideband; impulse radio; coherent; non-coherent; synchronization; low power; template-based correlation

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This paper presents a non-coherent assisted synchronization mechanism for low data rate coherent impulse radio ultra-wide band (IR-UWB) receivers. The proposed hybrid scheme simplifies the coherent synchronization and reduces power consumption by utilizing a two-step acquisition mechanism. The receiver achieves enhanced energy efficiency while maintaining sensitivity benefits of coherent detection.
This paper presents a non-coherent assisted synchronization mechanism for low data rate coherent impulse radio ultra-wide band (IR-UWB) receivers. A two-step coarse and fine acquisition mechanism is utilized to simplify the coherent synchronization and minimize the total required packet length. This hybrid scheme reduces the total power consumption of the receiver. The reception of a UWB packet begins with an energy efficient non-coherent synchronization portion in on-off keying (OOK) modulation non-coherent acquisition. This reduces the search space for the coherent reception by first finding the best integration window that has the most energy of the received signal. Afterwards, the receiver searches coherently in binary phase shift keying (BPSK) modulation within only the pre-selected integration window instead of the whole symbol time. Self-mixing and template-based correlation are utilized for the non-coherent and coherent reception, respectively. Most of the front-end blocks are shared between the coherent and non-coherent modes, including the LNA, mixer, and the baseband circuitry that follows to minimize the total power consumption of the receiver. A differential architecture including a low noise amplifier (LNA), a mixer, a fast start-up template generator, an integrator, and a differential comparator are utilized for the receiver front-end. A prototype of the proposed receiver operating from 3.5 to 5 GHz over four bands, each spaced by 500 MHz, is implemented in 65-nm CMOS technology. The proposed receiver architecture achieves a -68 dBm, -70.5 dBm, and -70.8 dBm sensitivity at a 10-3 BER at 50 MHz pulse repetition frequency (PRF) in the non-coherent, coherent, and proposed hybrid synchronization modes, respectively. The receiver consumes 6.8 mW and 8.8 mW in the non-coherent and coherent mode, respectively, when continuously ON. Using its novel synchronization mechanism, the receiver can reduce the ON time of the receiver by 68% and 34% in order to coherently synchronize and receive a 100-bit and 1024-bit payload, respectively. As a result, the energy per useful bit (EPUB) of the receiver is reduced by a factor of 2.9 from 1.24 nJ/b to 422 pJ/b for 100-bit payloads, and by a factor of 1.5 from 309 pJ/b to 204 pJ/b for 1024-bit payloads, increasing energy efficiency while maintaining the sensitivity benefits of coherent detection.

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