A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current-Mismatch Wide-Frequency-Acquisition Technique

This paper reports a reference-less frequency-detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 [(Gb/s)/mu s] and an energy efficiency of 1.3 pJ/bit.

Automated summary

This paper presents a BBCDR circuit, which is a reference-less and frequency-detector-less single-loop bang-bang clock and data recovery circuit, with the feature of wide frequency acquisition. The circuit uses a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter for quarter-rate operation, achieving a capture range of 110.4%. By utilizing a deliberate-current-mismatch charge pump pair, the circuit eliminates power-hungry circuits and adopts a single-sided capture scheme in the frequency detection characteristic. With a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in 32 bands. Implementing this circuit in a 65-nm CMOS, the BBCDR covers a broad data rate range from 10.8 to 37.4 Gb/s, achieving high acquisition speed and energy efficiency.