3D SRAM Macro Design in 3D Nanofabric Process Technology

In this paper, we introduce a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology. The 3D Nanofabric technology is based on enabling the processing of N stack of identical layers simultaneously regardless of the number of stacked layers which consequently reduces the fabrication cost as well as the footprint of SRAM macros. To enable simultaneous patterning of stacked layers, 3D Nanofabric requires circuit topology and layout that rely on a single layer where the device channel, poly, and metal wires are all embedded without any other crossing than the gate on top of the device channel. Accordingly, we modify the layouts of the conventional SRAM bit-cell and periphery circuits which are complex and contain several metal crossings. Furthermore, we propose a new overall organization of the 3D SRAM macro that incorporates a stack of multiple identical layers each consisting of an equal size 2D array of bit-cells and the periphery circuits. We show that the proposed 3D Nanofabric SRAM macro offers 71.2% footprint gain and 36.3% read access speed improvement compared to equal size 2D SRAM macro in 3 nm FinFET.

Automated summary

In this paper, a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology is introduced. The design utilizes the 3D Nanofabric technology to process multiple stacked layers simultaneously, reducing fabrication cost and SRAM macro footprint. The layouts of conventional SRAM bit-cell and periphery circuits are modified to accommodate the requirements of 3D Nanofabric, and a new organization of the 3D SRAM macro is proposed. Experimental results show significant improvements in footprint gain and read access speed compared to 2D SRAM macro in 3 nm FinFET.