A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive VoltageTime-Voltage Converter

This article presents a 12-effective number of bits (ENOB) second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage-timevoltage (V-T-V) converter. The proposed NS-SAR ADC uses a V-T-V converter to provide an accurate open-loop gain stage for the active residue process. By relying on the capacitor and current ratios, the gain of the V-T-V converter is inherently PVTinsensitive. Therefore, no calibration is needed, and an aggressive noise transfer function (NTF) can be realized. Moreover, the V-T-V converter consumes only dynamic power, making the ADC more efficient. The proposed design was fabricated in the TSMC 90-nm 1P9M CMOS process with a core area of 429.7 x 90.7 mu m(2). At 1-V supply voltage and 10-MS/s sampling rate, the ADC achieved a signal to noise and distortion ratio (SNDR) of 73.8 dB, and the corresponding ENOB is about 12-bit at 625-kHz input signal bandwidth. The total power consumption is 71.4 mu W, resulting in a Walden figure of merit (FoMW) and Schreier figure of merit (FoMS) of 14.2 fJ/c-s and 173.2 dB, respectively.

Automated summary

This article presents a 12-effective number of bits (ENOB) second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage-time-voltage (V-T-V) converter. The proposed NS-SAR ADC uses a V-T-V converter for accurate open-loop gain stage and achieves an aggressive noise transfer function (NTF) without the need for calibration. The ADC achieves a SNDR of 73.8 dB and an ENOB of 12-bit with a power consumption of 71.4 µW in the TSMC 90-nm 1P9M CMOS process.