A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain Scale Alignment

This article presents a power efficient and process, voltage, and temperature (PVT) robust pipelined successive approximation register (SAR) analog-to-digital converter (ADC) that quantizes signals in both voltage and time domains. In this work, a low-power SAR ADC is adopted as the coarse quantizer, while a ring-configured time-to-digital converter (TDC) is utilized in the fine quantizer to improve the linearity and power efficiency. In addition, the ring TDC also participates in the voltage-to-time conversion to guarantee that one-lap delay in the ring TDC is aligned with the least quantization step in the voltage domain. As a result, an auto-scale alignment between voltage and time domains is promised regardless of PVT variations. The ADC prototype IC was fabricated in a 22-nm CMOS technology. When measured at 260 MS/s, the ADC achieves 60.5-dB signal-to-noise and distortion ratio (SNDR) and 77-dB spurious-free dynamic range (SFDR) with a Nyquist input, while consuming 0.97 mW from a 0.8-V power supply. The calculated Walden and Schreier figures-of-merit (FoMs) are 4.27 fJ/conversion step and 171.8 dB, respectively.

Automated summary

This article presents a power efficient and configurable pipelined SAR ADC that quantizes signals in both voltage and time domains to address PVT variations. The ADC utilizes a low-power SAR ADC as the coarse quantizer and a ring-configured TDC as the fine quantizer to improve linearity and power efficiency. The ADC prototype achieves high performance and consumes low power with a Nyquist input.