Journal
IEEE ELECTRON DEVICE LETTERS
Volume 44, Issue 10, Pages 1644-1647Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2023.3310614
Keywords
Atomic layer deposition; oxygen annealing; InZnO TFTs; indium zinc oxide; high mobility; DIBL; thin-film transistors; positive-bias stress; stability
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This study presents the fabrication of high-performance atomic layer deposited ultrathin Indium Zinc Oxide thin-film transistors with a short channel length. The transistors exhibit excellent electrical characteristics, including high current and optimized threshold voltage. Moreover, they demonstrate ultra-low drain-induced barrier lowering performance and good gate stability.
The high-performance atomic layer deposited(ALD) ultrathin (similar to 2 nm) amorphous InZnO (a-IZO, indium:Zinc approximate to 6:4) channel thin-film transistors (TFTs) with a short channel length (L-ch) of 50 nm were presented. Further-more, the gate stability was evaluated using temperature-dependent positive-bias stress (PBS) tests for the IZOTFTs up to 3.5 MV/cm. The short channel TFTs exhibited excellent electrical characteristics, with high Ionexceeding360 mu A/mu m (@V-G=2V), and an optimized threshold voltage (V-th) of similar to 0.11 V. In particular, the ultra-low drain-induced barrier lowering (DIBL) performance of 16 mV/Vwas presented and matched with technology computer aided design (TCAD) estimation. The activation energy ofdevice degradation was extracted to better understand the mechanism. The extracted high field effect channelmobility (mu(FE)) of 43.6 cm(2)/V-s in conjunction with the low V-th shifts of 12.4 mV (@ 3.5 MV/cm; V-th+2V) for 5000sPBS test at 25degree celsius exhibited the excellent performancescombining channel mobility and gate stability reported foroxide semiconductor TFT.
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