Energy-efficient approximate full adders for error-tolerant applications

Low-power consumption is of utmost importance in modern digital systems-on-chip. Approximate computing is a technique used in error-tolerant applications such as multimedia and machine learning to reduce power. This technique creates an appropriate trade-off between performance and accuracy. Adders, as the core of the computing blocks for many digital systems, have a significant impact on their efficiency. This paper attempts to design new approximate full adders with power as the main optimization goal. The proposed circuits are simulated with HSPICE using CMOS and FinFET technologies at 45 nm and 14 nm technology nodes respectively. The simu-lation results show that on average, the proposed FAs offer 18% and 22% improvements in the dynamic energy and the static power compared to their recent counterparts. Moreover, at the system level, the proposed designs provide sufficient accuracy for real computational applications such as Gaussian filter, discrete cosine transform, and k-means clustering.

Automated summary

This paper investigates the design of low-power approximate full adders and demonstrates their improvements in dynamic energy and static power through simulations. Furthermore, the proposed designs are shown to provide sufficient accuracy for real computational applications.