Electrical microstructure evolution of CaCu3Ti4O12 (CCTO) ceramics: From resistive and core shell-like to semiconducting grains

We show that CaCu3Ti4O12 (CCTO) ceramics present either giant (>104) or moderate (-102) dielectric permittivity e' at room temperature (RT), depending on the grains resistivity. By sintering at 980 & DEG;C, a highly resistive bulk is obtained (resistivity of 5.8 G & omega; cm) and no giant e' is verified. A semiconducting phase develops into the grains by sintering at 1050 & DEG;C, with a remaining thin resistive phase, hence forming a core-shell bulk microstructure. By increasing the sintering temperature to 1100 & DEG;C, the semiconducting phase of the bulk grows at the expenditure of the insulating shell, forming the well-known Internal Barrier Layer Capacitance (IBLC) structure. It is therefore proved that the giant e' in CCTO ceramics is linked to the grain boundaries dielectric response whose manifestation becomes resolved at RT when the bulk phase is semiconducting in nature. Such an effect is thermally originated during processing and related to Cu migration towards grain boundaries.

Automated summary

We demonstrated that the dielectric permittivity e' of CaCu3Ti4O12 (CCTO) ceramics can reach giant (>104) or moderate (-102) values at room temperature depending on the resistivity of the grains. A highly resistive bulk with no giant e' was obtained by sintering at 980°C. Sintering at 1050°C resulted in the development of a semiconducting phase within the grains and a thin resistive phase, forming a core-shell bulk structure. Increasing the sintering temperature to 1100°C led to the growth of the semiconducting phase at the expense of the insulating shell, forming the well-known Internal Barrier Layer Capacitance (IBLC) structure. This phenomenon is thermally originated and related to Cu migration towards grain boundaries.