4.5 Article

Design of soft-error resilient SRAM cell with high read and write stability for robust operations

Related references

Note: Only part of the references are listed.
Article Engineering, Electrical & Electronic

Energy-efficient radiation hardened SRAM cell for low voltage terrestrial applications

Govind Prasad et al.

Summary: In this paper, a 12T radiation-hardened SRAM cell is proposed, which outperforms the latest proposed counterparts. The simulation results demonstrate that the proposed cell has the lowest power loss and highest stability and soft error immunity, making it a promising candidate for future low voltage terrestrial applications.

MICROELECTRONICS JOURNAL (2022)

Article Engineering, Electrical & Electronic

Double-node-upset aware SRAM bit-cell for aerospace applications

Govind Prasad et al.

Summary: This paper proposes a radiation-hardened 13T SRAM cell that is capable of recovering from both SNUs and DNUs induced at any of its sensitive nodes. The cell has low power consumption, high critical charge, moderate area overhead, and better stability.

MICROELECTRONICS RELIABILITY (2022)

Article Engineering, Electrical & Electronic

A triple-node upset self-healing latch for high speed and robust operation in radiation-prone harsh-environment

Sandeep Kumar et al.

Summary: With continuous advancement in technology, a novel triple-node-upset self-healing latch is proposed in this study, which performs robust operation in harsh radiation environment. Through simulation validation, it is shown that the proposed latch offers highest speed of operation and has the lowest cost in terms of power-delay-area-product.

MICROELECTRONICS RELIABILITY (2022)

Article Engineering, Electrical & Electronic

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

Aibin Yan et al.

Summary: This paper proposes two SRAM cells, QCCS and SCCS, for improving the vulnerability to soft errors. The QCCS cell achieves self-recoverability from SNUs at low cost, while the SCCS cell robustly keeps stored values by constructing a large error-interceptive feedback loop. Simulation results demonstrate the effectiveness of the proposed cells, which outperform state-of-the-art hardened cells in terms of access time, power dissipation, and silicon area overhead.

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY (2022)

Article Engineering, Electrical & Electronic

Soft-Error-Aware SRAM for Terrestrial Applications

Govind Prasad et al.

Summary: A novel low-cost and write-enhanced SRAM cell, LWS14T, is proposed for protection against soft errors, showing better critical charge, stability, and writability compared to traditional cells.

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY (2021)

Article Computer Science, Hardware & Architecture

A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications

Sandeep Kumar et al.

Summary: This paper introduces a single event double node upset self-healing latch designed to meet the high-robustness requirement of applications in a harsh radiation environment. Through fault injection simulation and analysis, it is shown that the proposed latch can self-heal from radiation events, with superior performance in speed, power consumption, and area compared to existing SEDNU resilient latches.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2021)

Article Engineering, Electrical & Electronic

Single-Event Multiple Effect Tolerant RHBD14T SRAM Cell Design for Space Applications

C. H. Naga Raghuram et al.

Summary: SRAM is used as a memory storage element susceptible to radiation-induced SEUs, making robust SRAM bit-cell design a difficult task. As transistor sizes move into nanometer regimes, a new challenge of SEMEs has emerged in SRAM design. The proposed RHBD14T SRAM bit-cell is immune to SEUs and delivers higher SEME critical charge compared to state-of-the-art RHBD SRAM bit-cells.

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY (2021)

Article Engineering, Electrical & Electronic

Soft-Error Resilient Read Decoupled SRAM With Multi-Node Upset Recovery for Space Applications

Soumitra Pal et al.

Summary: The article presents a radiation-hardened SRAM cell, SRRD12T, that can recover from SEUs and SEMNUs in space. With a read decoupled design, SRRD12T exhibits the highest read stability but slightly longer read delay compared to other cells. Additionally, SRRD12T has lower hold power consumption and higher write ability than most comparison cells, with a shorter write delay than RHD12T and RHMP12T.

IEEE TRANSACTIONS ON ELECTRON DEVICES (2021)

Article Engineering, Electrical & Electronic

Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications

Soumitra Pal et al.

Summary: In this paper, a Soft-Error-Aware 14T (SEA14T) SRAM cell for aerospace applications is proposed, which outperforms other radiation-hardened SRAM cells in terms of recovery from single-event upsets and multi-node upsets. The proposed cell also exhibits shorter read and write delays, higher read stability, higher write ability, and lower hold power consumption, although at the cost of slightly larger area overhead.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2021)

Letter Computer Science, Information Systems

Design of a high-performance 12T SRAM cell for single event upset tolerance

Chunhua Qi et al.

SCIENCE CHINA-INFORMATION SCIENCES (2021)

Proceedings Paper Computer Science, Hardware & Architecture

A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design

Sandeep Kumar et al.

Summary: This paper presents the design of a radiation-hardened latch that is capable of self-healing from single event upsets at all internal and output nodes. The proposed latch utilizes clock-gating based C-elements and input-splitting inverters to achieve high speed and excellent self-healing capability. Compared to existing SEU self-healing latches, the proposed latch demonstrates significant improvements in speed, power consumption, and PDAP, as well as lower PVT sensitivity.

34TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT 2021) (2021)

Article Computer Science, Hardware & Architecture

Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications

Qiang Zhao et al.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2020)

Article Engineering, Aerospace

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments

Aibin Yan et al.

IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS (2020)

Article Engineering, Electrical & Electronic

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance

Jing Guo et al.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2020)

Article Engineering, Electrical & Electronic

Power optimized SRAM cell with high radiation hardened for aerospace applications

Govind Prasad et al.

MICROELECTRONICS JOURNAL (2020)

Article Engineering, Electrical & Electronic

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

Jianwei Jiang et al.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2019)

Article Computer Science, Hardware & Architecture

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

Chunyu Peng et al.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2019)

Article Engineering, Electrical & Electronic

Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications

Vishal Sharma et al.

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS (2019)

Article Engineering, Electrical & Electronic

Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications

Sayeed Ahmad et al.

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS (2018)

Article Computer Science, Hardware & Architecture

Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

Mohsen Raji et al.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2017)

Article Engineering, Electrical & Electronic

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS

Aibin Yan et al.

MICROELECTRONICS JOURNAL (2017)

Article Engineering, Electrical & Electronic

A Highly Reliable Memory Cell Design Combined With Layout-Level Approach to Tolerant Single-Event Upsets

Chunhua Qi et al.

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY (2016)

Article Engineering, Electrical & Electronic

Low power and robust memory circuits with asymmetrical ground gating

Hailong Jiao et al.

MICROELECTRONICS JOURNAL (2016)

Article Computer Science, Hardware & Architecture

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

Jing Guo et al.

IEEE TRANSACTIONS ON RELIABILITY (2015)

Article Engineering, Electrical & Electronic

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology

Jing Guo et al.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2014)

Article Engineering, Electrical & Electronic

Underground Experiment and Modeling of Alpha Emitters Induced Soft-Error Rate in CMOS 65 nm SRAM

Sebastien Martinie et al.

IEEE TRANSACTIONS ON NUCLEAR SCIENCE (2012)

Article Computer Science, Hardware & Architecture

Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS

Sheng Lin et al.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2011)

Review Engineering, Electrical & Electronic

Basic mechanisms and modeling of single-event upset in digital microelectronics

PE Dodd et al.

IEEE TRANSACTIONS ON NUCLEAR SCIENCE (2003)