Design of soft-error resilient SRAM cell with high read and write stability for robust operations

This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-16T) to provide complete resilience to single event upsets (SEU). The proposed cell is complete resilient to SEU at any sensitive node and also shows recovery from the double-node-upset to its fixed internal node pair. Owing to its separate read path through an internal node, the proposed cell offers the highest read-stability, 6.8 times higher than the state-of-the-art cell RHD-14T. The proposed cell also shows the fastest write operation and its write access time is 1.6 times less compared to the recently proposed cell SCCS-18T. In addition, the proposed cell has 1.7-times higher write stability compared to state-of-the-art cell HP-12T. The SERSC-16T cell also shows moderate leakage power dissipation, which is 1.5 times less compared to the SCCS-18T cell. Moreover, the proposed cell shows the best figure of merit and the most negligible probability of SEU occurrence among all state of the art radiation hardened SRAM cells.

Automated summary

This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-16T) that provides complete resilience to single event upsets (SEU). The proposed cell is resilient to SEU at any sensitive node and also recovers from double-node-upsets. It offers the highest read-stability, fastest write operation, and the most negligible probability of SEU occurrence among radiation hardened SRAM cells.