Journal
IEEE EMBEDDED SYSTEMS LETTERS
Volume 15, Issue 2, Pages 113-116Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LES.2022.3218168
Keywords
Field-programmable gate array (FPGA); high-level synthesis (HLS); reinforcement learning (RL)
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Reinforcement learning is a method where an agent interacts with the environment to maximize rewards based on sequential decisions. It is widely used in various domains but requires large data processing and computational power. The letter proposes a FPGA-based accelerator for the Markov decision process, achieving over 7x acceleration compared to the original version.
In reinforcement learning (RL) an agent interacts with the environment based on sequential decisions. This agent receives a reward from the environment according to decisions and tries to maximize the reward. RL is used in several domains, such as production, autonomous driving, business management, education, games, healthcare, natural language processing, robotics, and among others. RL methodologies require processing large volumes of data and computational power. To speed up these applications, field-programmable gate array (FPGA) are widely employed in the literature. This letter proposes an accelerator for theMarkov decision process (MDP) implemented in the AI-Toolbox public library using high-level synthesis tools, using the tiger-antelope problem as use case. Our approach shows an acceleration greater than 7x compared to the original version.
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