A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

Article Computer Science, Hardware & Architecture

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving-82.2-dBc REF Spur and-255-dB FOM

Zunsong Yang et al.

Summary: This brief introduces an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) that effectively suppresses the spur-induced BFSK modulation and shortens the settling time with the incorporation of a push-pull sub-sampling phase detector and a low-power fast-locking FLL. The prototyped SS-PLL in 65-nm CMOS demonstrates excellent performance, including a reference spur of -82.2 dBe, integrated jitter of 64.9 fs(rms), and in-band PN of -128.4 dBc/Hz at 1-MHz offset. The SS-PLL consumes only 7.5 mW, with FLL accounting for 90 μW.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2022)

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Article Computer Science, Hardware & Architecture

A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications

Chih-Wei Tsai et al.

Summary: An all-digital delay-locked loop (ADDLL) suitable for DDR1-DDR5 applications is proposed, combining synchronous mirror delay and DLL advantages for dynamic tracking. Experimental chip results show an operating range from 0.1 to 2.7 GHz, with excellent performance for high-speed digital signal applications.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2021)

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Article Computer Science, Hardware & Architecture

A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links

Ching-Yuan Yang et al.

Summary: A clock-deskewing circuit (CDC) utilizing a master-slave delay-locked loop (MSDLL) configuration is proposed to synchronize clocks for cascading core-to-core links without the need for any dummy elements for phase compensation. The CDC with dual-locking provides mismatch-insensitive compensation for interconnected wires, input/outputs (IOs), and clock buffers. The use of a digital-selection folded coarse-fine voltage-controlled delay line (FCF-VCDL) in the MSDLL allows for a wide range of operations and adaptive power dissipation reduction.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2021)

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Proceedings Paper Engineering, Electrical & Electronic

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics

Hojun Yoon et al.

Summary: This paper introduces a quadrature error corrector (QEC) for next generation DRAM interface, which corrects duty-cycle error and 4-phase skew simultaneously to achieve high speed operation. The prototype chip demonstrates less than 1.84 degrees phase error at 12.8 Gb/s and has a correctable range of 100.5 degrees within a lock-time of 120 ns.

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) (2021)

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Proceedings Paper Engineering, Electrical & Electronic

A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector using Bangbang Duty-Cyle-Detector

Jincheol Sim et al.

Summary: The text discusses the use of a bang-bang duty cycle detector in a duty cycle corrector to correct the duty cycle of a 1-3.2 GHz clock, using an average codes method to mitigate detector offset. The system is designed in CMOS 28nm process with a maximum duty cycle error of 1.5%.

2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) (2021)

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Proceedings Paper Engineering, Electrical & Electronic

A 0.8-3.5 GHz Shared TDC-based Fast-Lock All-Digital DLL with a Built-in DCC

Taeyeon Kim et al.

Summary: This paper presents a new TDC-based fast-lock all-digital DLL with a built-in DCC, achieving fast lock time and high operation frequency. The proposed architecture allows for speed up to 3.5 GHz, improving traditional DLLs with limited frequency and slow lock time.

2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) (2021)

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Article Engineering, Electrical & Electronic