A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

Automated summary

This article presents a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL has a dual delay line structure, with each delay line having a coarse adjustment and a fine adjustment unit, and corresponding control units to minimize mismatch between the delay lines, thus avoiding the need for a complicated duty cycle correction (DCC) circuit. A frequency divider was included to widen the range of input clock duty cycle adjustment. Furthermore, a simple clock synthesis circuit was introduced for synthesizing the required clock. The designed DLL utilized the 25 nm process and operated at a voltage of 1.2 V. Simulation results demonstrated that, at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.