4.7 Article

High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator

Journal

IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
Volume 11, Issue 2, Pages 527-533

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TETC.2022.3202113

Keywords

Magnetic tunneling; Transistors; Neural networks; Logic gates; CNTFETs; Delays; Convolutional neural networks; Spintronic; logic-in-memory; hardware accelerator; binarized neural network; GAA-CNTFET

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This paper proposes a BNN hardware accelerator based on a nonvolatile XNOR/XOR circuit designed using MTJ and GAA-CNTFET devices. The design eliminates external memory access, reducing data transmission delay and power dissipation. It has low energy consumption, making it suitable for battery-operated devices. The combinational read circuitry of the design exhibits high robustness to process variations. Simulation results show a negligible logical error rate and high network accuracy even with significant process variations. The proposed hardware accelerator outperforms its state-of-the-art counterparts in terms of power, PDP, and area with improvements of at least 13%, 29%, and 41%.
The convolutional neural network (CNN) is a significant part of the artificial intelligence (AI) systems widely used in different tasks. The binarized neural networks (BNNs) reduce power consumption and hardware overhead to answer the demands for using AI in power-limited applications. In this paper, a BNN hardware accelerator is proposed. The proposed approach is based on a novel nonvolatile XNOR/XOR circuit designed using the magnetic tunnel junction (MTJ) and gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) devices. The nonvolatility of the proposed design leads to the elimination of external memory access that significantly decreases the data transmission delay and power dissipation. Moreover, it consumes low energy, which is very critical in battery-operated devices. Furthermore, the combinational read circuitry of the proposed design leads to high robustness to process variations. According to the simulation results, our proposed design has a logical error rate of 0.0164%, which is negligible and offers a significantly high network accuracy even in the presence of significant process variations. Our proposed hardware accelerator provides at least 13%, 29%, and 41% improvements regarding power, power delay product (PDP), and area compared to its state-of-the-art counterparts.

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