Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications.

Automated summary

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes that come after the planar MOSFET reached its scaling limit. SOI FinFET devices combine the advantages of both FinFET and SOI devices and can be further enhanced by SiGe channels. This study presents an optimization strategy for the Ge fraction in SiGe Channels of SGOI FinFET devices. Simulation results of RO circuits and SRAM cells demonstrate that adjusting the Ge fraction can enhance the performance and power efficiency of different circuits for various applications.