Interface Optimization and Performance Enhancement of Er2O3-Based MOS Devices by ALD-Derived Al2O3 Passivation Layers and Annealing Treatment

In this paper, the effect of atomic layer deposition (ALD)-derived Al2O3 passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited Er2O3 high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived Al2O3 passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 x 10(-9) A/cm(2) and the smallest interfacial density of states (Dit) of 2.38 x 10(12) cm(-2) eV(-1) have been achieved in the Al2O3/Er2O3/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed Al2O3/Er2O3/Si gate stacks at 450 degrees C have demonstrated superior dielectric properties with a leakage current density of 1.38 x 10(-9) A/cm(2). At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated.

Automated summary

This paper investigates the impact of atomic layer deposition (ALD)-derived Al2O3 passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited Er2O3 high-k gate dielectrics on Si substrate. X-ray photoelectron spectroscopy (XPS) analyses reveal that the ALD-derived Al2O3 passivation layer effectively prevents the formation of low-k hydroxides and optimizes the gate dielectric properties. Electrical performance measurements demonstrate that the Al2O3/Er2O3/Si MOS capacitor achieves the lowest leakage current density of 4.57 x 10(-9) A/cm(2) and the smallest interfacial density of states (Dit) of 2.38 x 10(12) cm(-2) eV(-1) due to the optimized interface chemistry. Furthermore, annealing the Al2O3/Er2O3/Si gate stacks at 450 degrees C improves the dielectric properties with a leakage current density of 1.38 x 10(-9) A/cm(2), and different conduction mechanisms of MOS devices under various stack structures are investigated systematically.