An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant Depended on Search Algorithm in HEVC

This paper illustrates the Quadrant Search Algorithm identified with the Zero motion previously established inclination for motion evaluation towards the High-Efficiency Video Coding (HEVC) unit and to its hardware architecture. To diminish the calculation time and to obtain the elevated efficient output HEVC is employed. Quadrant depended search algorithm is one of the quickest algorithm to decide the most astounding interaction at the time of recent block on to the reference block. Zero Motion Prejudgment (ZMP) technique is employed to expose whether a block is motion or static and to lessen the calculation difficulty of search algorithm. Contrasted to Adaptive Rood Pattern Search and Diamond Search, Quadrant related search algorithm employs fewer searches to determine the best matching block. The hardware architecture for an Field Programmable Gate Array implementation of the Quadrant depended on search algorithm with ZMP is proposed. Our proposed search algorithm minimizes the calculation complexity in the HEVC encoder. The full architecture is executed by means of Verilog HDL on Virtex-5 technology as well as a blend by means of Xilinx ISE Design Suite 14.5. The control utilization of the proposed design is reduced to 0.143W. Besides, the proposed design achieves the maximum operating frequency of 284.06 MHz.

Automated summary

This paper introduces a Quadrant Search Algorithm for motion evaluation in HEVC and its hardware architecture. It reduces calculation time and achieves higher output efficiency. Compared to other search algorithms, it employs fewer searches to determine the best matching block.