An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning

The growing computational demand in artificial intelligence calls for hardware solutions that are capable of in situ machine learning, where both training and inference are performed by edge computation. This not only requires extremely energy-efficient architecture (such as in-memory computing) but also memory hardware with tunable properties to simultaneously meet the demand for training and inference. Here we report a duplex device structure based on a ferroelectric field-effect transistor and an atomically thin MoS2 channel, and realize a universal in-memory computing architecture for in situ learning. By exploiting the tunability of the ferroelectric energy landscape, the duplex building block demonstrates an overall excellent performance in endurance (>10(13)), retention (>10 years), speed (4.8 ns) and energy consumption (22.7 fJ bit(-1) mu m(-2)). We implemented a hardware neural network using arrays of two-transistors-one-duplex ferroelectric field-effect transistor cells and achieved 99.86% accuracy in a nonlinear localization task with in situ trained weights. Simulations show that the proposed device architecture could achieve the same level of performance as a graphics processing unit under notably improved energy efficiency. Our device core can be combined with silicon circuitry through three-dimensional heterogeneous integration to give a hardware solution towards general edge intelligence. By integrating split ferroelectric capacitors with complementary characteristics in the same memory cell, this architecture tackles the problem of conflicting memory requirements for training and inference, which has long plagued edge intelligence applications.

Automated summary

A duplex device structure based on a ferroelectric field-effect transistor and an atomically thin MoS2 channel was developed, enabling a universal in-memory computing architecture for in situ learning. The device exhibited excellent performance in endurance, retention, speed, and energy consumption. It can be integrated with silicon circuitry to provide a hardware solution for general edge intelligence.