Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten

3D integration of III-V semiconductors with Si CMOS ishighly attractivesince it allows combining new functions such as photonic and analogdevices with digital signal processing circuitry. Thus far, most 3Dintegration approaches have used epitaxial growth on Si, layer transferby wafer bonding, or die-to-die packaging. Here we present low-temperatureintegration of InAs on W using Si3N4 templateassisted selective area metal-organic vapor-phase epitaxy (MOVPE).Despite growth nucleation on polycrystalline W, we can obtain a highyield of single-crystalline InAs nanowires, as observed by transmissionelectron microscopy (TEM) and electron backscatter diffraction (EBSD).The nanowires exhibit a mobility of 690 cm(2)/(V s), a low-resistive,Ohmic electrical contact to the W film, and a resistivity which increaseswith diameter attributed to increased grain boundary scattering. Theseresults demonstrate the feasibility for single-crystalline III-V back-end-of-lineintegration with a low thermal budget compatible with Si CMOS.

Automated summary

This article introduces a method of 3D integration of III-V semiconductors on Si CMOS using low-temperature Si3N4 template-assisted selective area metal-organic vapor-phase epitaxy (MOVPE). By observing with transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD), we can obtain high yield of single-crystalline InAs nanowires, which have a mobility of 690 cm(2)/(V s), low-resistive Ohmic electrical contact to the W film, and resistivity that increases with diameter due to increased grain boundary scattering. These results demonstrate the feasibility of single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.