Journal
JOURNAL OF PHYSICS D-APPLIED PHYSICS
Volume 56, Issue 32, Pages -Publisher
IOP Publishing Ltd
DOI: 10.1088/1361-6463/accfa9
Keywords
laser-to-chip coupling; three-dimensional taper; integrated photonic circuit; SU-8
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In this research, a 3D SU-8 tapered edge coupler is designed and simulated to effectively guide light from an edge-emitting semiconductor laser diode to a silicon waveguide, creating a hybrid on-chip silicon light source. The results show that this polymer taper significantly improves coupling efficiency for moderately thick silicon waveguides, achieving a coupling efficiency of 67% compared to 41% without the taper. The 3D finite-difference time-domain simulations also reveal wave transformation in the tapered coupler and input silicon waveguide. This cost-effective and easily fabricated coupler has potential applications in mass production of various silicon photonic chips.
In this work, we design and simulate a three-dimensional (3D) SU-8 tapered edge coupler for effectively guiding light from an edge-emitting semiconductor laser diode directly to a silicon waveguide to realize a hybrid on-chip silicon light source. A series of coupling efficiencies for the commonly used top silicon thicknesses of the silicon-on-insulator wafers from 220 to 3000 nm are obtained, showing that this polymer taper can largely improve the coupling efficiency when the silicon waveguide thickness is moderate, for instance, from 41% (with no taper) to 67% for the 700 nm- thick silicon waveguide under 1 mu m gap offset and relax the lateral misalignment tolerance to above one micron by suppressing the butt refractive index contrast and the mode mismatch between the laser diode and the silicon waveguide. Wave transformation inside the tapered coupler and the input silicon waveguide has also been revealed by 3D finite-difference time-domain simulations. This 3D tapered coupler is cost effective and easily fabricated which can have wide practical applications in massive production of various silicon photonic chips based on the present complementary metal-oxide-semiconductor foundry.
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