4.3 Article

Design of artificial neural network hardware accelerator

Journal

JOURNAL OF INSTRUMENTATION
Volume 18, Issue 4, Pages -

Publisher

IOP Publishing Ltd
DOI: 10.1088/1748-0221/18/04/C04013

Keywords

Digital electronic circuits; Digital signal processing (DSP)

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We have designed a scalable processor that can provide artificial neural network functionality and developed tools for automatic conversion of ANN models from TensorFlow to HDL code. The hardware, described in SystemVerilog, allows the processor to perform neural network calculations at a speed exceeding 100 MHz. Our software tool supports the translation of multilayer perceptron neural networks into state machine modules and can be dynamically reconfigured. The project aims to implement energy estimation for X-ray photons at the pixel level with higher accuracy than an ADC converter.
We present a design of the scalable processor capable of providing an artificial neural network (ANN) functionality and in-house developed tools for automatic conversion of an ANN model designed with the TensorFlow library into an HDL code. The hardware is described in SystemVerilog and the synthesized module of the processor can perform calculations of a neural network with the speed exceeding 100 MHz. Our in-house designed software tool for ANN conversion supports translation of an arbitrary multilayer perceptron neural network into a state machine module, which performs necessary calculations. It is also dynamically reconfigurable so that the ANN operating on the hardware can be changed after it is deployed as an ASIC. The project aims the in-pixel implementation towards an X-ray photon energy estimation. The energy estimation shall be delivered with accuracy that exceeds the accuracy of an ADC converter that feeds the ANN with data.

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