4.6 Article

A nonunit two-stage protection scheme for DC transmission lines in high-voltage DC grids

Publisher

ELSEVIER SCI LTD
DOI: 10.1016/j.ijepes.2022.108742

Keywords

Nonunit protection; Two -stage protection; Traveling wave; HVDC grid; High -resistance fault

Ask authors/readers for more resources

This paper proposes a novel nonunit two-stage protection method to address the issue of high-resistance faults. By analyzing the propagation process of fault traveling waves and the characteristic differences of waves generated by DCCBs, the method achieves rapid identification and clearing of faults, with high tolerance for high-resistance faults.
Nonunit protection is suitable for the primary protection of DC lines in high-voltage DC (HVDC) grids because of its rapidity. However, most existing nonunit protections are not sensitive enough for remote-end high-resistance faults. To solve this problem, a novel nonunit two-stage protection capable of tolerating high-resistance faults is proposed in this paper. First, the propagation process of a traveling wave (TW) generated by the fault is presented, revealing the insufficiency of fault TW-based protections to tolerate remote-end high-resistance faults. Then, the TW generated by the DC circuit breaker (DCCB) located on the opposite end is analyzed, and its characteristic difference between the internal and external faults is discussed. Moreover, the nonunit two-stage protection scheme that contains stage-I and stage-II protections is proposed. Stage-I protection rapidly identifies the closed-end and remote-end low-resistance faults using the fault TW. Stage-II protection identifies the remoteend high-resistance fault using the TW generated by the DCCB, and the fault clearing time is reduced by combining the DCCB operation. The protection criteria, setting principle and operation process of the proposed protection scheme are presented in detail. Finally, a large number of PSCAD/EMTDC simulations validate the excellent performance of the proposed scheme, including a high fault resistance tolerance, quick fault clearing time, and no requirements of excessive sampling frequency and complex mathematical operations.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.6
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available