A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS

This letter presents a 4 -level Pulse Amplitude Modulation (PAM -4) Feed Forward Equaliser (FFE) with a novel Internal Node Charge Controlled 1 -Unit Interval Pulse Generator (INCC 1UIPG). Partially segmented architecture and tailless 1 -stage front end are chosen to reduce the overall load capacitance for better bandwidth and power performance. The proposed INCC 1UIPG adopts a stacking -reduced structure and precisely controls the internal nodes, demonstrating advantages in speed, power, and jitter, showing better potential of working at a ultra -high baud rate. The wider bandwidth and faster transition edge allow the implementation of the equaliser working at 128Gbps with an area of 0.014 mm2 in 65 nm CMOS.

Automated summary

This article introduces a 4-level Pulse Amplitude Modulation (PAM-4) Feed Forward Equaliser (FFE) with a novel Internal Node Charge Controlled 1-Unit Interval Pulse Generator (INCC 1UIPG). Partially segmented architecture and tailless 1-stage front end are used to reduce load capacitance for better bandwidth and power performance. The proposed INCC 1UIPG adopts a stacking-reduced structure and precise control of internal nodes, demonstrating advantages in speed, power, and jitter, showing better potential for working at ultra-high baud rates. The wider bandwidth and faster transition edge enable the equalizer to operate at 128Gbps with an area of 0.014 mm2 in 65 nm CMOS.