Design of a high performance CNFET 10T SRAM cell at 5nm technology node

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5nm technology node, through optimization design and simulation analysis to select optimum gate widths of transistors to ensure best performance in terms of stability, speed and power consumption. We compare the proposed 10T CNFET SRAM with the optimized 6T CNFET SRAM in [9]. It was found that the timing and power characteristics of the proposed 10T SRAM cell is better than that of the 6T structure, the static power consumption is greatly reduced while the RSNM is improved by 93.5%, read and write EDP are improved by 68.5% and 96%, respectively.

Automated summary

This article presents a CNFET 10T SRAM cell based on Stanford Virtual Source model at the 5nm technology node. Through optimization design and simulation analysis, the optimum gate widths of transistors are selected to ensure the best performance in terms of stability, speed, and power consumption. The proposed 10T CNFET SRAM is compared with the optimized 6T CNFET SRAM, and it is found that the proposed 10T SRAM cell outperforms the 6T structure in terms of timing, power consumption, RSNM, read and write EDP.