4.8 Article

Fault Analysis of Inverter-Interfaced RESs Considering Decoupled Sequence Control

Journal

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 70, Issue 5, Pages 4820-4830

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2022.3181382

Keywords

Circuit faults; Analytical models; Fault currents; Mathematical models; Control systems; Transient analysis; Renewable energy sources; Decoupled sequence control (DSC); fault analysis; inverter-interfaced renewable energy sources (IIRESs)

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This article proposes a Laplace domain fault modeling method to investigate fault characteristics of grid-following inverter-interfaced renewable energy sources (IIRESs) employing decoupled sequence control (DSC). A detailed fault model of IIRESs with DSC is established, taking into account the high-order and coupling features of commonly used positive and negative sequence components calculation (PNSCC) modes. The model can explore the contributing factors of the IIRES's fault response within different fault phases.
To adapt to the operation under asymmetric conditions, an increasing number of grid-following inverter-interfaced renewable energy sources (IIRESs) start to employ the decoupled sequence control (DSC). However, due to the variety and complexity of the positive and negative sequence components calculation (PNSCC) modes used for DSC, the fault response of IIRESs with DSC has rarely been studied using the analytical method. To this end, this article proposes a Laplace domain fault modeling method to investigate fault characteristics of IIRESs with DSC. The high-order and coupling features of commonly used PNSCC modes are analyzed, and then they are taken into account to establish a detailed fault model of IIRESs with DSC. To further apply the fault model to the practical fault analysis, different PNSCC modes are generalized to obtain a unified form, and thus a reduced-order fault model of IIRESs with DSC covering the complete fault phases can be yielded. Based on this model, contributing factors of the IIRES's fault response within different fault phases can be explored. Simulation and hardware-in-loop experiments indicate that this model can be applied to various fault scenarios with an error less than 7%, providing a theoretical foundation to support the protection scheme.

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