4.6 Article

Performance and Short-Circuit Reliability of SiC MOSFETs With Enhanced JFET Doping Design

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 70, Issue 5, Pages 2395-2402

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2023.3259925

Keywords

JFETs; Silicon carbide; MOSFET; Doping; Logic gates; Capacitance; Reliability; JFET doping concentration; JFET width; short-circuit (SC) reliability; silicon carbide (SiC) MOSFETs

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This article discusses the influence of the JFET width and JFET doping concentration on the static characteristics, C-V characteristics, and short-circuit (SC) reliability of 1.2-kV planar-gate silicon carbide (SiC) MOSFETs. The increase in JFET width leads to a decrease in specific ON-resistance, decrease in blocking voltage, and increase in reverse capacitance. The SC peak current initially increases and then decreases with an increase in JFET width, while the SC withstanding time keeps decreasing. Enhanced JFET doping is preferred as it improves the figure of merit and high-frequency figure of merit without sacrificing much SC reliability.
In this article, the influence of the JFET width and JFET doping concentration on the 1.2-kV planar-gate silicon carbide (SiC) MOSFETs' static characteristics, C-V characteristics, and short-circuit (SC) reliability is discussed. With the increase of the JFET width, the specific ON-resistance decreases first and then increases (but the quasi-saturated current continues to increase), the blocking voltage decreases, and the reverse capacitance increases. The SC tests under 400-V dc bus voltage are carried out to compare the SC capability of the devices. With the increase of the JFET width, the SC peak current first increases and then decreases, and the SC withstanding time keeps decreasing. The increase of peak current is due to the weaker electric field shielding effect by the P-well. With the further increase of the JFET width, the peak current decreases because the depletion layer appears in the middle position of the JFET region below the gate oxide and the channel density decreases with the wider JFET width. Compared with the winner of the traditional design, the winner with enhanced JFET doping is preferred because it achieves an increased Baliga's figure of merit (BFOM) by 15.9% and 1/high-frequency figure of merit (HF-FOM) by 84.2% without sacrificing too much SC reliability, which is more competitive.

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